This invention relates generally to signal decoders for decoding sequence codes such as the Viterbi algorithm decoder, and more particularly the invention relates to the add-compare-select (ACS) function processor in such decoders and the renormalization or rescaling of calculated path metrics in the ACS processor.
Convolutional encoding and Viterbi decoding are used to provide forward error correction in transmitted digital data and thus improve digital communication performance over a noisy transmission link. The convolutional encoder establishes a code tree relationship between input and output sequences. Each branch of the tree represents a single input symbol. Any input sequence traces out a specific path through the tree. Another way of viewing the code tree is the trellis diagram. The Viterbi algorithm attempts to find a path through the trellis using the maximum likelihood decision. The two paths entering each node of a trellis are compared, and the path with the best metric (minimum error) is selected. The other path is rejected since its likelihood can never exceed that of the selected path regardless of the subsequent received data. Thus, at any given time, there is only one path with the best metric entering into each current node of the trellis.
FIG. 1 is a block diagram of a Viterbi decoder and includes a branch metric unit (BMU) to calculate transition metrics .lambda. which are then accumulated recursively as path metrics in the add-compare-select (ACSU). The survivor trace unit (STU) processes the decisions made in the ACSU and TMU and gives out the decoded data. A high-speed Viterbi decoder implementation requires high-speed solutions for all three units. Since the TMU and SMU are of simple feed forward structure, parallel processing architectures are easily derived. However, the ASCU contains the nonlinear ACS-recursion which represents a bottleneck.
In most Viterbi designs, the ACS processor contains the most critical path which determines the speed of the decoder. Each ACS element includes two adders, a comparator, and a storage element. The two adders are used to add the values of the current state metrics to the new branch metrics for the upper and lower branches. The comparator then evaluates the results of the two adders and selects the smaller of the two metrics. The selected metric is then stored in a storage element as the next state metrics. The complexity of this circuit is linearly proportional to the number of bits used to represent the path metrics. The value of any path metric is limited.
Thus, a minimum effective cumulative metric range must be provided between the largest metric and the smallest metric. The present invention is directed to efficiently maintaining the effective cumulative metric range by renormalizing calculated path metrics in a timely manner and thereby increasing data rate throughput.